62 search results - page 5 / 13 » Leakage Minimization Technique for Nanoscale CMOS VLSI |
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
- The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce subthreshol...
DAC
2004
ACM
13 years 11 months ago
2004
ACM
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
A new technique has been proposed to improve the transient behavior of the on-chip/embedded voltage regulator. It is realized by introducing a dynamic leakage path at the driver s...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with ...