62 search results - page 6 / 13 » Leakage Minimization Technique for Nanoscale CMOS VLSI |
26
Voted
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
VLSID
2006
IEEE
14 years 7 months ago
2006
IEEE
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...