331 search results - page 11 / 67 » Limits on Multiple Instruction Issue |
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
MICRO
1999
IEEE
14 years 1 months ago
1999
IEEE
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
IJPP
2000
13 years 8 months ago
2000
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
HPCA
2005
IEEE
14 years 9 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...