331 search results - page 7 / 67 » Limits on Multiple Instruction Issue |
MICRO
1993
IEEE
14 years 28 days ago
1993
IEEE
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
MICRO
1996
IEEE
14 years 1 months ago
1996
IEEE
For decades, the serialization constraints imposed by true data dependences have been regarded as an absolute limit--the dataflow limit--on the parallel execution of serial progra...
CJ
2006
13 years 8 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
ICCD
2005
IEEE
14 years 5 months ago
2005
IEEE
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
ISCA
1997
IEEE
14 years 11 days ago
1997
IEEE
As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate branch prediction. Because hardwa...