331 search results - page 8 / 67 » Limits on Multiple Instruction Issue |
APCSAC
2001
IEEE
14 years 14 days ago
2001
IEEE
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performanc...
ISCA
2011
IEEE
13 years 16 days ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
ISCA
1992
IEEE
14 years 27 days ago
1992
IEEE
This paper discusses three techniques useful in relaxing the constraints imposed by control flow on parallelism: control dependence analysis, executing multiple flows of control s...
PACS
2004
Springer
14 years 2 months ago
2004
Springer
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...