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IEEEPACT
2006
IEEE
14 years 1 months ago
Overlapping dependent loads with addressless preload
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir
ISCA
2010
IEEE
170views Hardware» more  ISCA 2010»
14 years 13 days ago
Relax: an architectural framework for software recovery of hardware faults
As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whe...
Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaral...
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 11 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
WWW
2002
ACM
14 years 8 months ago
A web-based resource migration protocol using WebDAV
The web's hyperlinks are notoriously brittle, and break whenever a resource migrates. One solution to this problem is a transparent resource migration mechanism, which separa...
Michael P. Evans, Steven Furnell
GECCO
2008
Springer
186views Optimization» more  GECCO 2008»
13 years 8 months ago
A pareto following variation operator for fast-converging multiobjective evolutionary algorithms
One of the major difficulties when applying Multiobjective Evolutionary Algorithms (MOEA) to real world problems is the large number of objective function evaluations. Approximate...
A. K. M. Khaled Ahsan Talukder, Michael Kirley, Ra...