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DATE
2009
IEEE
149views Hardware» more  DATE 2009»
14 years 2 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
IEEECIT
2010
IEEE
13 years 6 months ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...
ESTIMEDIA
2004
Springer
14 years 1 months ago
A queuing-theoretic performance model for context-flow system-on-chip platforms
Abstract—Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which pre...
Rami Beidas, Jianwen Zhu
ICC
2007
IEEE
102views Communications» more  ICC 2007»
14 years 2 months ago
A Scalable Wireless Channel Emulator for Broadband MIMO Systems
: This paper addresses the issue of designing scalable prototypes for multi input multi output (MIMO) wireless channel emulation. To date, emulators are extending single input sing...
Hamid Eslami, Ahmed M. Eltawil
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
14 years 5 days ago
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
Bharat P. Dav