79 search results - page 12 / 16 » Linear Programming based Techniques for Synthesis of Network... |
149
click to vote
CC
2007
Springer
15 years 11 months ago
2007
Springer
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
175
click to vote
DAC
2006
ACM
16 years 6 months ago
2006
ACM
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
153
click to vote
PLDI
2003
ACM
15 years 10 months ago
2003
ACM
We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal b...
141
click to vote
VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
152
click to vote
DAC
2006
ACM
16 years 6 months ago
2006
ACM
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource...