303 search results - page 60 / 61 » Link-Time Improvement of Scheme Programs |
ISCA
2010
IEEE
14 years 22 days ago
2010
IEEE
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
IEEEPACT
2000
IEEE
14 years 19 hour ago
2000
IEEE
In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value predicti...
ISCA
2000
IEEE
14 years 16 hour ago
2000
IEEE
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
SAS
2000
Springer
13 years 11 months ago
2000
Springer
As compilers increasingly rely on optimizations to achieve high performance, the effectiveness of source level debuggers for optimized code continues to falter. Even if values of s...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
The need to reuse the performance macromodels of an analog circuit topology challenges existing regression based modeling techniques. A model of good reusability should have a num...