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» Linking codesign and reuse in embedded systems design
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IPPS
2007
IEEE
14 years 2 months ago
Splice: A Standardized Peripheral Logic and Interface Creation Engine
Recent advancements in FPGA technology have allowed manufacturers to place general-purpose processors alongside user-configurable logic gates on a single chip. At first glance, ...
Justin Thiel, Ron K. Cytron
DAC
2006
ACM
14 years 8 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 1 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
EURODAC
1995
IEEE
131views VHDL» more  EURODAC 1995»
13 years 11 months ago
System level design, a VHDL based approach
A hierarchical system design flow was developed to facilitate concurrent development and Time-to-Market reductions. The system design flow provides for codesign of (embedded) driv...
Joris van den Hurk, Edwin Dilling
GECCO
2004
Springer
136views Optimization» more  GECCO 2004»
14 years 1 months ago
System Level Hardware-Software Design Exploration with XCS
Abstract. The current trend in Embedded Systems (ES) design is moving towards the integration of increasingly complex applications on a single chip. An Embedded System has to satis...
Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciu...