1929 search results - page 372 / 386 » Load Balancing with Memory |
MICRO
2002
IEEE
14 years 1 months ago
2002
IEEE
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
ICS
2001
Tsinghua U.
14 years 1 months ago
2001
Tsinghua U.
We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism. Operation-based prefetchers predict the series of operation...
HIPC
1999
Springer
14 years 1 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
NSDI
2010
13 years 10 months ago
2010
In many enterprises today, WAN optimizers are being deployed in order to eliminate redundancy in network traffic and reduce WAN access costs. In this paper, we present the design ...
BMCBI
2006
13 years 9 months ago
2006
Background: Molecular biologists work with DNA databases that often include entire genomes. A common requirement is to search a DNA database to find exact matches for a nondegener...