Sciweavers

141 search results - page 10 / 29
» Load Execution Latency Reduction
Sort
View
HPCA
2005
IEEE
14 years 7 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
HIPEAC
2007
Springer
14 years 1 months ago
Compiler-Assisted Memory Encryption for Embedded Processors
A critical component in the design of secure processors is memory encryption which provides protection for the privacy of code and data stored in off-chip memory. The overhead of ...
Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy
DATE
2010
IEEE
131views Hardware» more  DATE 2010»
14 years 17 days ago
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions
—This paper presents a design space exploration of a selective load value prediction scheme suitable for energyaware Simultaneous Multi-Threaded (SMT) architectures. A load value...
Arpad Gellert, Gianluca Palermo, Vittorio Zaccaria...
EUROPAR
2010
Springer
13 years 8 months ago
Profile-Driven Selective Program Loading
Abstract. Complex software systems use many shared libraries frequently composed of large off-the-shelf components. Only a limited number of functions are used from these shared li...
Tugrul Ince, Jeffrey K. Hollingsworth
ICIP
2003
IEEE
14 years 9 months ago
On the scalability of an image transcoding proxy server
Image transcoding proxies are used to improve Web browsing over low bandwidth networks by adapting content-rich web images to bandwidth-constrained clients. Such transcoding proxi...
Anubhav Savant, Nasir D. Memon, Torsten Suel