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CODES
2010
IEEE
13 years 5 months ago
Worst-case performance analysis of synchronous dataflow scenarios
Synchronous Dataflow (SDF) is a powerful analysis tool for regular, cyclic, parallel task graphs. The behaviour of SDF graphs however is static and therefore not always able to ac...
Marc Geilen, Sander Stuijk
DATE
2008
IEEE
103views Hardware» more  DATE 2008»
14 years 2 months ago
Compositional design of isochronous systems
The synchronous modeling paradigm provides strong execution correctness guarantees to embedded system design while making minimal environmental assumptions. In most related framew...
Jean-Pierre Talpin, Julien Ouy, Loïc Besnard,...
GLVLSI
2006
IEEE
126views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Hardware/software partitioning of operating systems: a behavioral synthesis approach
In this paper we propose a hardware real time operating system (HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the P...
Sathish Chandra, Francesco Regazzoni, Marcello Laj...
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 1 months ago
Dynamic code overlay of SDF-modeled programs on low-end embedded systems
In this paper we propose a dynamic code overlay technique of synchronous data-flow (SDF) –modeled program for low-end embedded systems which lack MMUsupport. With this technique...
Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Myoung-m...
ASYNC
2000
IEEE
86views Hardware» more  ASYNC 2000»
14 years 1 days ago
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
George S. Taylor, Simon W. Moore, Steve Wilcox, Pe...