1321 search results - page 3 / 265 » Logic Simulation Using Networks of State Machines |
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical...
ICCD
1995
IEEE
13 years 11 months ago
1995
IEEE
– This paper describes a new technique for extracting clock-level finite state machines(FSMs) from transistor netlists using symbolic simulation. The transistor netlist is prepr...
EH
1999
IEEE
1999
IEEE
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
13 years 11 months ago
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
IJCNN
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— Hardware implementations of Spiking Neural Networks are numerous because they are well suited for implementation in digital and analog hardware, and outperform classic ...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
The optimal state minimization problem is to select a reduced state machine having the best logic implementation over all possible state reductions and encodings. A recent algorit...