233 search results - page 19 / 47 » Logic design for low-voltage low-power CMOS circuits |
DAC
2005
ACM
13 years 10 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
—This paper presents a 2GHz 8-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). Nonlinear current steering digital to analog converter (DAC) has been utilized to con...
DATE
1999
IEEE
14 years 28 days ago
1999
IEEE
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
DAC
1997
ACM
14 years 24 days ago
1997
ACM
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
ASYNC
1997
IEEE
14 years 25 days ago
1997
IEEE
The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described in this paper. The main advantage of temary logic is the easy realisation of...