233 search results - page 22 / 47 » Logic design for low-voltage low-power CMOS circuits |
ASYNC
2006
IEEE
14 years 2 months ago
2006
IEEE
Distributed sensor networks, human body implants, and hand-held electronics have tight energy budgets that necessitate low power circuits. Most of these devices include an analog-...
ISVLSI
2008
IEEE
14 years 3 months ago
2008
IEEE
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS pro...
PATMOS
2005
Springer
14 years 2 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
Abstract - A comprehensive study of ultra high-speed currentmode logic (CML) buffers and regenerative CML latches will be illustrated. A new design procedure to systematically desi...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
— We describe an analog VLSI circuit implementing spike-driven synaptic plasticity, embedded in a network of integrate-and-fire neurons. This biologically inspired synapse is hi...