120 search results - page 16 / 24 » Logical Filtering |
SIPS
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents an error compensation method for truncated multiplication. From two n-bit operands, the operator produces an n-bit product with small error compared to the 2n-b...
JOLPE
2010
13 years 7 months ago
2010
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft e...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
EH
1999
IEEE
14 years 27 days ago
1999
IEEE
-- This paper describes the operation of a field programmable gate array (FPGA), the basics of current mode logic, and examines the idea of creating a SiGe heterojunction bipolar (...
CADE
2007
Springer
14 years 9 months ago
2007
Springer
This paper combines predictive labeling with dependency pairs and reports on its implementation. Our starting point is the method of proving termination of rewrite systems using se...