This paper presents an error compensation method for truncated multiplication. From two n-bit operands, the operator produces an n-bit product with small error compared to the 2n-b...
Romain Michard, Arnaud Tisserand, Nicolas Veyrat-C...
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft e...
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
-- This paper describes the operation of a field programmable gate array (FPGA), the basics of current mode logic, and examines the idea of creating a SiGe heterojunction bipolar (...
This paper combines predictive labeling with dependency pairs and reports on its implementation. Our starting point is the method of proving termination of rewrite systems using se...