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» Logical Foundations for Data Integration
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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
14 years 1 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
ICLP
1999
Springer
14 years 1 months ago
CLAIRE: Combining Sets, Search, and Rules to Better Express Algorithms
This paper presents a programming language that includes paradigms that are usually associated with declarative languages, such as sets, rules and search, into an imperative (funct...
Yves Caseau, François-Xavier Josset, Fran&c...
DAC
1997
ACM
14 years 1 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
ECAI
1994
Springer
14 years 28 days ago
Combining the Lazy Label Evaluation with Focusing Techniques in an ATMS
For large problems the ATMS often becomes the main resource consumer in any reasoning system. We propose an architecture (the 2vATMS) that combines the advantages of two techniques...
Mugur M. Tatar
EMNETS
2007
14 years 23 days ago
SeeDTV: deployment-time validation for wireless sensor networks
Deployment of a wireless sensor network (WSN) system is a critical step because theoretical models and assumptions often differ from real environmental characteristics and perform...
H. Liu, Leo Selavo, John A. Stankovic