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DAC
2003
ACM
14 years 24 days ago
Efficient compression and application of deterministic patterns in a logic BIST architecture
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...
LANMR
2007
13 years 9 months ago
Equivalence for the G3'-stable models semantics
Abstract We study the notion of strong equivalence between two disjunctive logic programs under the G3-stable model semantics, also called the P-stable semantics, and we show how s...
José Luis Carballido, José Arrazola,...
ASPDAC
2004
ACM
151views Hardware» more  ASPDAC 2004»
14 years 29 days ago
Combinatorial group testing methods for the BIST diagnosis problem
— We examine an abstract formulation of BIST diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of erroneous test vector...
Andrew B. Kahng, Sherief Reda
VTS
2002
IEEE
138views Hardware» more  VTS 2002»
14 years 13 days ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
ICCAD
2009
IEEE
101views Hardware» more  ICCAD 2009»
13 years 5 months ago
Compacting test vector sets via strategic use of implications
As the complexity of integrated circuits has increased, so has the need for improving testing efficiency. Unfortunately, the types of defects are also becoming more complex, which...
Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan...