980 search results - page 24 / 196 » Logical Testing |
ICCAD
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
MTDT
2000
IEEE
13 years 12 months ago
2000
IEEE
In this work, we present the application of Generalized Linear Feedback Shift Registers (GLFSRs) for generation of patterns for pseudo-random memory Built-In SelfTest (BIST). Rece...
SBCCI
2009
ACM
14 years 6 days ago
2009
ACM
Because of the aggressive scaling of integrated circuits and the given limits of atomic scales, circuit designers have to become more and more aware of the arising reliability and...
VTS
1997
IEEE
13 years 11 months ago
1997
IEEE
A stress procedure for reliability screening, SHOrt Voltage Elevation (SHOVE) test, is analyzed here. During SHOVE, test vectors are run at higher-than-normal supply voltage for a...
ISQED
2003
IEEE
14 years 24 days ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...