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ATS
2005
IEEE
164views Hardware» more  ATS 2005»
13 years 9 months ago
A Family of Logical Fault Models for Reversible Circuits
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional ...
Ilia Polian, Thomas Fiehn, Bernd Becker, John P. H...
ET
2002
77views more  ET 2002»
13 years 7 months ago
Reusing Scan Chains for Test Pattern Decompression
The paper presents a method for testing a system-on-achip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test ar...
Rainer Dorsch, Hans-Joachim Wunderlich
DAC
1999
ACM
13 years 12 months ago
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...
Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. ...
AAAI
2008
13 years 10 months ago
Hyperequivalence of Logic Programs with Respect to Supported Models
Recent research in nonmonotonic logic programming has focused on program equivalence relevant for program optimization and modular programming. So far, most results concern the st...
Miroslaw Truszczynski, Stefan Woltran
BIRTHDAY
2004
Springer
14 years 28 days ago
Pure Type Systems in Rewriting Logic: Specifying Typed Higher-Order Languages in a First-Order Logical Framework
Abstract. The logical and operational aspects of rewriting logic as a logical framework are tested and illustrated in detail by representing pure type systems as object logics. Mor...
Mark-Oliver Stehr, José Meseguer