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TCAD
2002
134views more  TCAD 2002»
13 years 7 months ago
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures
As IC densities are increasing, cluster-based FPGA architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-based architecture is one in which...
Ian G. Harris, Russell Tessier
DATE
2005
IEEE
235views Hardware» more  DATE 2005»
14 years 1 months ago
Challenges in Embedded Memory Design and Test
Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to upd...
Erik Jan Marinissen, Betty Prince, Doris Keitel-Sc...
CADE
2011
Springer
12 years 7 months ago
Deciding Security for Protocols with Recursive Tests
Abstract. Security protocols aim at securing communications over public networks. Their design is notoriously difficult and error-prone. Formal methods have shown their usefulness ...
Mathilde Arnaud, Véronique Cortier, St&eacu...
CHARME
2003
Springer
97views Hardware» more  CHARME 2003»
14 years 24 days ago
Convergence Testing in Term-Level Bounded Model Checking
We consider the problem of bounded model checking of systems expressed in a decidable fragment of first-order logic. While model checking is not guaranteed to terminate for an ar...
Randal E. Bryant, Shuvendu K. Lahiri, Sanjit A. Se...
ITC
2003
IEEE
108views Hardware» more  ITC 2003»
14 years 25 days ago
Backplane Test Bus Applications For IEEE STD 1149.1
Prior to the mid 1980s, the dominance of through-hole packaging of integrated circuits (ICs) provided easy access to nearly every pin of every chip on a printed circuit board. Pro...
Clayton Gibbs