—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...
Udo Krautz, Matthias Pflanz, Christian Jacobi 0002...
In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate...
This paper presents an evolutionary approach to learning a fuzzy logic controller(FLC) employed for reactive behaviour control of Sony legged robots. The learning scheme is divided...
We present a novel multiple-threshold circuit using resonant-tunneling diodes (RTDs). The logic operation is based on detecting a switching sequence in the RTD circuit. This schem...
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...