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» Loop Parallelization in the Polytope Model
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IPPS
2009
IEEE
14 years 2 months ago
Accelerating HMMer on FPGAs using systolic array based architecture
HMMer is a widely-used bioinformatics software package that uses profile HMMs (Hidden Markov Models) to model the primary structure consensus of a family of protein or nucleic aci...
Yanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan ...
ASPDAC
1998
ACM
86views Hardware» more  ASPDAC 1998»
13 years 12 months ago
Parallelization in Co-Compilation for Configurable Accelerators
— The paper introduces a novel co-compiler and its “vertical” parallelization method, including a general model for co-operating host/accelerator platforms and a new parallel...
Jürgen Becker, Reiner W. Hartenstein, Michael...
HPCC
2007
Springer
14 years 1 months ago
Parallel Database Sort and Join Operations Revisited on Grids
Based on the renowned method of Bitton et al. (see [1]) we develop a concise but comprehensive analytical model for the well-known Binary Merge Sort, Bitonic Sort, Nested-Loop Join...
Werner Mach, Erich Schikuta
CCE
2005
13 years 7 months ago
Use of parallel computers in rational design of redundant sensor networks
A general method to design optimal redundant sensor network even in the case of one sensor failure and able to estimate process key parameters within a required accuracy is propos...
Carine Gerkens, Georges Heyen
FPL
2001
Springer
123views Hardware» more  FPL 2001»
14 years 3 days ago
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
This paper presents new achievements on the automatic mapping of algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable ...
João M. P. Cardoso, Horácio C. Neto