114 search results - page 7 / 23 » Loop Parallelization in the Polytope Model |
FPL
2003
Springer
14 years 25 days ago
2003
Springer
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
EUROPAR
2001
Springer
14 years 3 days ago
2001
Springer
Abstract. Traditional code optimization techniques treat loops as nonpredictable structures and do not consider expressions containing array accesses for optimization. We show that...
ASAP
2010
IEEE
13 years 9 months ago
2010
IEEE
Data-flow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of data-flow, termed synchronous data...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Optimizing compilers apply numerous interdependent optimizations, leading to the notoriously difficult phase-ordering problem — that of deciding which transformations...
IPPS
1996
IEEE
13 years 11 months ago
1996
IEEE
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...