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FPL
2006
Springer
96views Hardware» more  FPL 2006»
13 years 11 months ago
High Speed Document Clustering in Reconfigurable Hardware
High-performance document clustering systems enable similar documents to automatically self-organize into groups. In the past, the large amount of computational time needed to clu...
G. Adam Covington, Charles L. G. Comstock, Andrew ...
MAM
2006
124views more  MAM 2006»
13 years 7 months ago
Design optimization and space minimization considering timing and code size via retiming and unfolding
The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such a...
Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, M...
IPPS
1999
IEEE
13 years 11 months ago
Cascaded Execution: Speeding Up Unparallelized Execution on Shared-Memory Multiprocessors
Both inherently sequential code and limitations of analysis techniques prevent full parallelization of many applications by parallelizing compilers. Amdahl's Law tells us tha...
Ruth E. Anderson, Thu D. Nguyen, John Zahorjan
DAC
2000
ACM
14 years 8 months ago
Hardware-software co-design of embedded reconfigurable architectures
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph ...
FPL
2003
Springer
95views Hardware» more  FPL 2003»
14 years 17 days ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra