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HPCA
2005
IEEE
14 years 1 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
CORR
2008
Springer
108views Education» more  CORR 2008»
13 years 7 months ago
Restricted Mobility Improves Delay-Throughput Trade-offs in Mobile Ad-Hoc Networks
Abstract-- In this paper, we analyze asymptotic delaythroughput trade-offs in mobile ad-hoc networks comprising heterogeneous nodes with restricted mobility. We show that node spat...
Michele Garetto, Emilio Leonardi
CONPAR
1994
13 years 11 months ago
A Framework for Resource-Constrained Rate-Optimal Software Pipelining
The rapid advances in high-performancecomputer architectureand compilationtechniques provide both challenges and opportunitiesto exploitthe rich solution space of software pipeline...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
CODES
2006
IEEE
14 years 1 months ago
Integrated analysis of communicating tasks in MPSoCs
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
Simon Schliecker, Matthias Ivers, Rolf Ernst
CASES
2007
ACM
13 years 11 months ago
Hierarchical coarse-grained stream compilation for software defined radio
Software Defined Radio (SDR) is an emerging embedded domain where the physical layer of wireless protocols is implemented in software rather than the traditional application speci...
Yuan Lin, Manjunath Kudlur, Scott A. Mahlke, Trevo...