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ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
14 years 17 days ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
ICPPW
2006
IEEE
14 years 3 months ago
Towards a Source Level Compiler: Source Level Modulo Scheduling
Modulo scheduling is a major optimization of high performance compilers wherein The body of a loop is replaced by an overlapping of instructions from different iterations. Hence ...
Yosi Ben-Asher, Danny Meisler
GLVLSI
1997
IEEE
110views VLSI» more  GLVLSI 1997»
14 years 1 months ago
Algorithm and Hardware Support for Branch Anticipation
Multi-dimensional systems containing nested loops are widely used to model scientific applications such as image processing, geophysical signal processing and fluid dynamics. Ho...
Ted Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Pa...
ICPADS
2006
IEEE
14 years 3 months ago
Efficient Compile-Time Task scheduling for Heterogeneous Distributed Computing Systems
Efficient task scheduling is essential for obtaining high performance in heterogeneous distributed computing systems (or HeDCSs). Because of its key importance, several scheduling...
Mohammad I. Daoud, Nawwaf N. Kharma
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
14 years 1 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha