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VLSID
1999
IEEE
99views VLSI» more  VLSID 1999»
13 years 11 months ago
Array Index Allocation under Register Constraints in DSP Programs
Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algor...
Anupam Basu, Rainer Leupers, Peter Marwedel
ICS
1993
Tsinghua U.
13 years 11 months ago
The EM-4 Under Implicit Parallelism
: The EM-4 is a supercomputer that offers very fast inter processor communication and support for multi threading. In this paper we demonstrate that the EM-4, Together with an auto...
Lubomir Bic, Mayez A. Al-Mouhamed
CN
2008
83views more  CN 2008»
13 years 7 months ago
Mitigating transient loops through interface-specific forwarding
Under link-state routing protocols such as OSPF and IS
Srihari Nelakuditi, Zifei Zhong, Junling Wang, Ram...
ICCD
2005
IEEE
97views Hardware» more  ICCD 2005»
14 years 4 months ago
Temperature-Sensitive Loop Parallelization for Chip Multiprocessors
In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to re...
Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T....
ISCAS
2006
IEEE
93views Hardware» more  ISCAS 2006»
14 years 1 months ago
Phase-tracking loop based on delta-sigma oversampling architecture
Abstract— This paper presents a new oversampling architecture for implementing phase-tracking loop that is commonly utilized for position sensors such that synchro, resolver, and...
Yuichiro Orino, Minoru Kuribayashi Kurosawa, Takas...