52 search results - page 5 / 11 » Low Power BIST Based on Scan Partitioning |
DAC
1999
ACM
14 years 8 months ago
1999
ACM
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
VTS
2002
IEEE
14 years 11 days ago
2002
IEEE
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
DFT
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
ISQED
2010
IEEE
14 years 18 days ago
2010
IEEE
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...