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LCTRTS
2007
Springer
14 years 1 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
14 years 1 months ago
Automatic ADL-based operand isolation for embedded processors
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
Anupam Chattopadhyay, B. Geukes, David Kammler, Er...
ASPDAC
2004
ACM
129views Hardware» more  ASPDAC 2004»
14 years 29 days ago
Instruction buffering exploration for low energy VLIWs with instruction clusters
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
Tom Vander Aa, Murali Jayapala, Francisco Barat, G...
FORMATS
2009
Springer
14 years 2 months ago
Exploiting Timed Automata for Conformance Testing of Power Measurements
For software development, testing is still the primary choice for investigating the correctness of a system. Automated testing is of utmost importance to support continuous integra...
Matthias Woehrle, Kai Lampka, Lothar Thiele
ISCAS
1999
IEEE
113views Hardware» more  ISCAS 1999»
13 years 11 months ago
Energy efficient software through dynamic voltage scheduling
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...
Gangadhar Konduri, James Goodman, Anantha Chandrak...