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GLVLSI
2010
IEEE
189views VLSI» more  GLVLSI 2010»
14 years 19 days ago
8Gb/s capacitive low power and high speed 4-PWAM transceiver design
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
CONEXT
2008
ACM
13 years 9 months ago
Towards high performance virtual routers on commodity hardware
Modern commodity hardware architectures, with their multiple multi-core CPUs and high-speed system interconnects, exhibit tremendous power. In this paper, we study performance lim...
Norbert Egi, Adam Greenhalgh, Mark Handley, Micka&...
VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
14 years 1 months ago
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors
The 3-2, 4-2 and 5-2 compressors are the basic components in many applications, in particular partial product summation in multipliers. In this paper novel architectures and desig...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...
PATMOS
2005
Springer
14 years 1 months ago
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications
In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural level, by using extensive clock and ...
Philippe Manet, David Bol, Renaud Ambroise, Jean-D...
DATE
2007
IEEE
74views Hardware» more  DATE 2007»
14 years 1 months ago
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the var...
Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosi...