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ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 1 months ago
A non-uniform cache architecture for low power system design
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
Tohru Ishihara, Farzan Fallah
CODES
2004
IEEE
13 years 11 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
ATS
2009
IEEE
185views Hardware» more  ATS 2009»
14 years 2 months ago
Customized Algorithms for High Performance Memory Test in Advanced Technology Node
Embedded memory quality is critical to overall chip quality. New defect mechanisms that occur at advanced process nodes (65nm and below) are often more pronounced in memories due ...
Shomo Chen, Ning Huang, Ting-Pu Tai, Actel Niu
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
14 years 28 days ago
Layered, Multi-Threaded, High-Level Performance Design
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas
ALGOSENSORS
2004
Springer
14 years 1 months ago
WiseMAC: An Ultra Low Power MAC Protocol for Multi-hop Wireless Sensor Networks
WiseMAC is a medium access control protocol designed for wireless sensor networks. This protocol is based on non-persistent CSMA and uses the preamble sampling technique to minimiz...
Amre El-Hoiydi, Jean-Dominique Decotignie