155 search results - page 21 / 31 » Low Power Techniques for Digital GaAs VLSI |
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input...
DICTA
2008
13 years 9 months ago
2008
Recently, semantic image retrieval has attracted large amount of interest due to the rapid growth of digital image storage. However, existing approaches have severe limitations. I...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
ISLPED
2009
ACM
14 years 5 days ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...