155 search results - page 6 / 31 » Low Power Techniques for Digital GaAs VLSI |
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a g...
GLVLSI
2000
IEEE
13 years 12 months ago
2000
IEEE
A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy r...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
DFT
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
ISVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...