155 search results - page 7 / 31 » Low Power Techniques for Digital GaAs VLSI |
VTC
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper we present extremely flexible and low power digital binary ASK, PSK, and FSK demodulator architectures for short-range applications that uses limiter amplifier (i...
CORR
2002
Springer
13 years 7 months ago
2002
Springer
-- This paper introduces a novel method for synthesizing digital circuits derived from Binary Decision Diagrams (BDDs) that can yield to reduction in power dissipation. The power r...
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
High-level power design presents a complex, multiobjective problem that involves the simultaneous optimisation of competing criteria such as speed, area and power. It is difficult...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
This paper discusses a number of circuit techniques which address the DC and AC distortion performance of a low power current steering Digital-to-Analog Converter design. The desi...
GLVLSI
2003
IEEE
14 years 23 days ago
2003
IEEE
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...