89 search results - page 11 / 18 » Low Power Testing of VLSI Circuits: Problems and Solutions |
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
GLVLSI
2003
IEEE
14 years 27 days ago
2003
IEEE
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
ISLPED
1997
ACM
13 years 11 months ago
1997
ACM
In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...