3799 search results - page 134 / 760 » Low Power or High Performance |
111
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
—This paper presents a 2GHz 8-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). Nonlinear current steering digital to analog converter (DAC) has been utilized to con...
133
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ASYNC
2002
IEEE
15 years 9 months ago
2002
IEEE
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
147
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MOBIQUITOUS
2007
IEEE
15 years 10 months ago
2007
IEEE
—This paper discusses the design and implementation of an ultra low power embedded GPS receiver node for use in remote monitoring situations where battery life is of the utmost i...
136
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ISCAS
2002
IEEE
15 years 9 months ago
2002
IEEE
Pre-designed configurable platforms, possessing microprocessors, memories, and numerous peripherals on a single chip, are increasing in popularity in embedded system design. Platf...
154
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TVLSI
2002
15 years 4 months ago
2002
: Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low...