Low-power clock distribution using multiple voltages and reduced swings

: Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low power clock tree by distributing the clock signal at a lower voltage, and translating it to a higher voltage at the utilization points. Two low power schemes are used: reduced swing and multiple supply voltages. We analyze the issue of tree construction and present conclusions relevant to various technology generations according to the NTRS. Our experimental results show that power savings of an average of 45% are possible for a 0.25

• Type: Journal
• Year: 2002
• Where: TVLSI
• Authors: Jatuchai Pangjun, Sachin S. Sapatnekar
• Keywords: Multiple Supply Voltages, Supply Voltage, TVLSI 2002, Voltage