3799 search results - page 139 / 760 » Low Power or High Performance |
114
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ICASSP
2009
IEEE
15 years 11 months ago
2009
IEEE
Due to their computational efficiency and strong empirical performance, semidefinite relaxation (SDR)–based algorithms have gained much attention in multiple–input multiple...
117
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
117
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ISLPED
1995
ACM
15 years 8 months ago
1995
ACM
We argue that the clocked-CMOS (C2MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market...
120
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ISCA
1997
IEEE
15 years 8 months ago
1997
IEEE
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
116
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EUROPAR
2008
Springer
15 years 6 months ago
2008
Springer
We explore different prefetch distance-degree combinations and very simple, low-cost adaptive policies on a superscalar core with a high bandwidth, high capacity on-chip memory hie...