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HPCA
2005
IEEE
14 years 1 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
ISCAS
2005
IEEE
159views Hardware» more  ISCAS 2005»
14 years 1 months ago
A low power FPGA routing architecture
— Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important crite...
Somsubhra Mondal, Seda Ogrenci Memik
FPL
2005
Springer
103views Hardware» more  FPL 2005»
14 years 1 months ago
Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications
Domain-specific heterogeneous reconfigurable arrays provide high performance over generic Field Programmable Gate Arrays (FPGAs) while maintaining the flexibility for that particu...
Sajid Baloch, Imran Ahmed, Tughrul Arslan, Adrian ...
ISVLSI
2008
IEEE
149views VLSI» more  ISVLSI 2008»
14 years 2 months ago
Uncriticality-Directed Low-Power Instruction Scheduling
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
Shingo Watanabe, Toshinori Sato
BSN
2009
IEEE
141views Sensor Networks» more  BSN 2009»
14 years 2 months ago
Low-Complexity, High-Throughput Multiple-Access Wireless Protocol for Body Sensor Networks
Wireless systems that form a body-area network must be made small and low power without sacrificing performance. To achieve high-throughput communication in low-cost wireless bod...
Seung-mok Yoo, Chong-Jing Chen, Pai H. Chou