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IPPS
1998
IEEE
15 years 8 months ago
Evaluation of a Low-Power Reconfigurable DSP Architecture
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an archit...
Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marl...
ISLPED
2000
ACM
111views Hardware» more  ISLPED 2000»
15 years 8 months ago
Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Variou...
Khurram Muhammad, Robert B. Staszewski, Poras T. B...
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
15 years 9 months ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt
GLVLSI
2006
IEEE
112views VLSI» more  GLVLSI 2006»
15 years 10 months ago
A design methodology for temperature variation insensitive low power circuits
Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology base...
Ranjith Kumar, Volkan Kursun
ICCD
2004
IEEE
114views Hardware» more  ICCD 2004»
16 years 27 days ago
Low Energy, Highly-Associative Cache Design for Embedded Processors
Many embedded processors use highly associative data caches implemented using a CAM-based tag search. When high-associativity is desirable, CAM designs can offer performance advan...
Alexander V. Veidenbaum, Dan Nicolaescu