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MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
15 years 8 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
15 years 10 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
IWUC
2004
15 years 5 months ago
On Uncertainty in Context-Aware Computing: Appealing to High-Level and Same-Level Context for Low-Level Context Verification
There is an inherent chasm between the real-world and the world that can be perceived by computer systems, yielding uncertainty and ambiguity in system perceived context, with cons...
Amir Padovitz, Seng Wai Loke, Arkady B. Zaslavsky
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
16 years 27 days ago
Vdd programmability to reduce FPGA interconnect power
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
Fei Li, Yan Lin, Lei He
ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
15 years 7 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn