3799 search results - page 86 / 760 » Low Power or High Performance |
139
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HPCA
2003
IEEE
16 years 4 months ago
2003
IEEE
Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effectiv...
128
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IPPS
1999
IEEE
15 years 8 months ago
1999
IEEE
Existing low-latency protocols make unrealistically strong assumptions about reliability. This allows them to achieve impressive performance, but also prevents this performance bei...
136
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CORR
2010
Springer
15 years 4 months ago
2010
Springer
We consider wireless networks that can be modeled by multiple access channels in which all the terminals are equipped with multiple antennas. The propagation model used to account...
114
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DATE
1998
IEEE
15 years 8 months ago
1998
IEEE
Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at...
143
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CF
2005
ACM
15 years 6 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...