240 search results - page 2 / 48 » Low energy asynchronous architectures |
FPL
2003
Springer
14 years 27 days ago
2003
Springer
We discuss high-performance programmable asynchronous pipeline arrays (PAPAs). These pipeline arrays are coarse-grain field programmable gate arrays (FPGAs) that realize high data...
ISCA
2002
IEEE
14 years 18 days ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
This paper presents for the first time low energy simultaneous memory and register allocation. A minimum cost network flow approach is used to efficiently solve for minimum energy...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
NOCS
2010
IEEE
13 years 6 months ago
2010
IEEE
A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global cloc...