The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthy...
Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increa...
Milena Milenkovic, Aleksandar Milenkovic, Emil Jov...
Multitenant data infrastructures for large cloud platforms hosting hundreds of thousands of applications face the challenge of serving applications characterized by small data foo...
Aaron J. Elmore, Sudipto Das, Divyakant Agrawal, A...
In order to take advantage of the low entry cost of the future public ATM (asynchronous transfer mode) network with shared facilities, it is highly desirable to interconnect diffe...