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ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 1 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
DAC
2010
ACM
13 years 10 months ago
A probabilistic and energy-efficient scheduling approach for online application in real-time systems
This work considers the problem of minimizing the power consumption for real-time scheduling on processors with discrete operating modes. We provide a model for determining the ex...
Thorsten Zitterell, Christoph Scholl
IEEEINTERACT
2003
IEEE
14 years 24 days ago
High Performance Code Generation through Lazy Activation Records
For call intensive programs, function calls are major bottlenecks during program execution since they usually force register contents to be spilled into memory. Such register to m...
Manoranjan Satpathy, Rabi N. Mahapatra, Siddharth ...
CVPR
2007
IEEE
13 years 7 months ago
PrivacyCam: a Privacy Preserving Camera Using uCLinux on the Blackfin DSP
Considerable research work has been done in the area of surveillance and biometrics, where the goals have always been high performance, robustness in security and cost optimizatio...
Ankur Chattopadhyay, Terrance E. Boult
CODES
2008
IEEE
14 years 2 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava