51 search results - page 2 / 11 » Low overhead fault-tolerant FPGA systems |
FPGA
2003
ACM
14 years 26 days ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
– The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for dupl...
IPPS
2003
IEEE
14 years 28 days ago
2003
IEEE
This work presents a new switching mechanism to tolerate arbitrary faults in interconnection networks with a negligible implementation cost. Although our routing technique can be ...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
Fault-tolerant distributed real-time systems are presently facing a lot of new challenges. Although many techniques provide effective masking of node failures on the architectural...
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
: Cluster systems gain more and more importance as a platform for parallel computing. In this area the power of the system is strongly coupled with the performance of the network, ...