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CPHYSICS
2007
106views more  CPHYSICS 2007»
13 years 7 months ago
The way towards thermonuclear fusion simulators
In parallel to the ITER project itself, many initiatives address complementary technological issues relevant to a fusion reactor, as well as many remaining scientific issues. One...
A. Bécoulet, Per Strand, H. Wilson, M. Roma...
MICRO
2008
IEEE
119views Hardware» more  MICRO 2008»
14 years 1 months ago
The StageNet fabric for constructing resilient multicore systems
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
14 years 1 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
HEURISTICS
2000
127views more  HEURISTICS 2000»
13 years 7 months ago
Fast, Efficient Equipment Placement Heuristics for Broadband Switched or Internet Router Networks
Planning and designing the next generation of IP router or switched broadband networks seems a daunting challenge considering the many complex, interacting factors affecting the p...
Joel W. Gannett
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
14 years 20 days ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood