173 search results - page 12 / 35 » Low power and low voltage CMOS digital circuit techniques |
GLVLSI
2002
IEEE
14 years 21 days ago
2002
IEEE
A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active...
VLSID
1996
IEEE
13 years 12 months ago
1996
IEEE
The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
Modern System-on-Chip (SoC) environments are swamped in high frequency noise that is generated by RF and digital circuits and propagated onto supply rails through capacitive coupli...
ICCAD
1996
IEEE
13 years 12 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
A subthreshold-leakage suppressed switched capacitor (SC) circuit based on super cut-off CMOS (SCCMOS) scheme is introduced. This scheme realizes low-voltage SC circuits using low...